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 M54HCT75 M74HCT75
4 BIT D TYPE LATCH
.HI .LOWPOWERDI .COMPATI .OUTPUTDRI .SYMMETRI .PI
GH SPEED tPD = 15 ns (TYP.) AT VCC = 5 V SSIPATION ICC = 2 A (MAX.) AT TA = 25 C BLE WITH TTL OUTPUTS VIH = 2 V (MIN.) VIL = 0.8 V (MAX.) VE CAPABILITY 10 LSTTL LOADS CAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) N AND FUNCTION COMPATIBLE WITH 54/74LS75
B1R (Plastic Package)
F1R (Ceramic Package)
DESCRIPTION TheM54/74HCT75 isahigh speedCMOS4-BITD-TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined withtrueCMOSlow power consumption. Itcontains two groups of 2-bit latches controlled by an enable input (G1 * 2 or G3 * 4). These two latch groups can be used indifferent circuits. Each latch has Q and Q outputs (1Q 4Q and 1Q - 4Q). The data applied to the data input is transfered to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input isretained atthe outputs. All inputs areequipped with protection circuits against static discharge and transient excessvoltage.This integrated circuit has input andoutput characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HCT75F1R M74HCT75M1R M74HCT75B1R M74HCT75C1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
NC = No Internal Connection
January 1993
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M54/M74HCT75
TRUTH TABLE
INPUTS D L H X G H H L OUTPUTS Q L H Qn Q H L Qn LATCH FUNCTION
IEC LOGIC SYMBOL
PIN DESCRIPTION
PIN No 1, 4, 11, 8 2, 3, 6, 7 4 13 15, 15, 10, 9 12 5 SYMBOL 1Q to 4Q 1D to 4D G3 * 4 G1 * 2 1Q to 4Q GND VCC NAME AND FUNCTION Complementary Latch Outputs Data Inputs Latch Enable Input, latches 3 and 4 Latch Enable Input, latches 1 and 2 Latch Outputs Ground (0V) Positive Supply Voltage
SCHEMATIC CIRCUIT
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK ICC IO or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
2/9
M54/M74HCT75
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time (VCC = 4.5 to 5.5V) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 500 Unit V V V
o o
C C ns
DC SPECIFICATIONS
Test Conditions Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 VI = IO=-20 A VIH or IO=-4.0 mA V IL VI = IO= 20 A VIH or IO= 4.0 mA V IL VI = VCC or GND VI = VCC or GND Per Input pin VI = 0.5V or V I = 2.4V Other Inputs at V CC or GND IO= 0 TA = 25 oC 54HC and 74HC Min. 2.0 Typ. Max. Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. 2.0 Max. Min. 2.0 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
V IL
0.8
0.8
0.8
V
V OH
4.4 4.18
4.5 4.31 0.0 0.17 0.1 0.26 0.1 2 2.0
4.4 4.13 0.1 0.33 1 20 2.9
4.4 4.10 0.1 V 0.4 1 40 3.0 A A mA V
VOL
Low Level Output Voltage
4.5
II ICC ICC
Input Leakage Current Quiescent Supply Current Additional worst case supply current
5.5 5.5 5.5
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M54/M74HCT75
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Test Conditions Symbol Parameter VCC (V) 4.5 4.5 TA = 25 C 54HC and 74HC Min. Typ. Max. 8 18 15 28
o
Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 19 35 22 42 ns Unit
tTLH tTHL tPLH tPHL tPLH tPHL tW(H) ts th CIN CPD (*)
Output Transition Time Propagation Delay Time (DATA-Q) Propagation Delay Time (G-Q) Minimum Pulse Width (G) Minimum Set-up Time Minimum Hold Time Input Capacitance Power Dissipation Capacitance
ns
4.5
21
33
41
50 ns
4.5 4.5 4.5
8 4
15 10 5
19 13 5 10
22 15 8 10
ns ns ns pF pF
5 61
10
(*) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD *VCC *fIN + ICC
SWITCHING CHARACTERISTICS TEST WAVEFORM
TEST CIRCUIT ICC (Opr)
* INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.
4/9
M54/M74HCT75
Plastic DIP16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
5/9
M54/M74HCT75
Ceramic DIP16/1 MECHANICAL DATA
mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276
DIM.
P053D
6/9
M54/M74HCT75
SO16 (Narrow) MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
7/9
M54/M74HCT75
PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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M54/M74HCT75
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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